Synopsys and A*STAR Forge a New Path for Advanced Chip Packaging Across Asia

Synopsys, a leading name in electronic design automation (EDA) and semiconductor IP, has launched a focused R&D partnership with Singapore’s Agency for Science, Technology and Research (A*STAR) to accelerate next-generation chip packaging. This collaboration is designed to address the intensifying industry pressures for greater compute density, improved energy efficiency and faster time-to-market by advancing 2.5D/3D packaging, heterogeneous integration and system-in-package (SiP) technologies across the Asia-Pacific ecosystem.

Why advanced chip packaging matters now

As Moore’s Law slows, advanced packaging has become a primary lever for performance gains. Packaging innovations-such as chiplets, through-silicon vias (TSVs) and interposers-allow designers to stack or tile dies, mix process nodes and integrate disparate functions without relying solely on monolithic scaling. For workloads from AI training to automotive electronics and 5G base stations, these techniques enable higher bandwidth, lower latency and improved power efficiency. Industry observers expect packaging to be a decisive factor in delivering next-generation systems, and partnerships between EDA vendors and research institutes are essential to close the gap from concept to manufacturable solutions.

Joint capabilities: what each partner brings

• Synopsys: System-level EDA flows, multi-die co-design and verification toolchains, IP platforms and virtual prototyping capabilities that support complex multi-die and SiP architectures.
• A*STAR: Materials research, reliability testing, pilot-line facilities and manufacturing know-how that enable lab-to-fab validation of new packaging materials and processes.

By pairing Synopsys’ software and design expertise with A*STAR’s experimental infrastructure and process development, the program aims to create validated packaging flows and reference design kits that regional foundries and OSATs (outsourced semiconductor assembly and test companies) can adopt quickly.

Technical priorities: from multi-die co-optimization to reliability

The collaboration focuses on several interlocking technical domains:

• 2.5D and 3D integration: Co-design methodologies that balance thermal, electrical and mechanical constraints for stacked or tiled die assemblies.
• Chiplet and SiP architectures: Modular reference designs and interoperability best practices to accelerate adoption of chiplet-based systems.
• Reliability and warpage control: Digital twin and virtual prototyping techniques to predict mechanical stresses, thermal cycling effects and long-term reliability before committing to expensive tape-outs.
• Materials and process innovation: New substrate materials, underfills and bonding approaches validated through joint labs and pilot runs.

Think of advanced packaging like urban planning: instead of sprawling outward (bigger transistors), designers build vertically and assemble neighborhoods of specialized blocks, each optimized for its role. Success requires coordinated planning tools, construction techniques and maintenance regimes-precisely the gap Synopsys and A*STAR intend to close together.

Roadmap and ecosystem initiatives

The partners have outlined a pragmatic roadmap that combines shared infrastructure, co-developed curricula and open collaboration with local industry. Key initiatives include:

• Joint testbeds and prototyping hubs in Singapore to shorten iteration cycles between design, material selection and manufacturing.
• Reference design kits (RDKs) and validated tool flows aligned with leading Asian foundries and OSATs for quicker technology transfer.
• Talent programs-courses, hands-on labs and internships-co-created with universities to grow a workforce conversant in system-level co-design, reliability physics and packaging process engineering.
• Standards and interoperability efforts to promote plug-and-play chiplet ecosystems and reduce integration friction among suppliers.

Practical outcomes for regional players

For fabs, OSATs and fabless companies across Asia, the collaboration offers tangible benefits: lower development risk through virtual qualification, faster prototyping via shared infrastructure and early access to cross-validated design/IP blocks. Startups and mid-size design houses can also leverage standardized RDKs to focus more on differentiation and less on reinventing complex integration flows.

Already, chiplet-based designs and advanced SiP approaches are appearing in many production and near-production AI accelerators and networking chips-demonstrating how validated packaging flows can compress time-to-market for performance-critical devices.

Building long-term capability: workforce and standards

Beyond technical deliverables, the partnership emphasizes human capital and ecosystem coherence. A*STAR’s training programs combined with Synopsys’ industry-grade tools aim to produce engineers who can navigate the multidisciplinary challenges of packaging-from material selection and thermo-mechanical analysis to system-level verification. Coupled with standards alignment, this effort seeks to create an interoperable, resilient regional cluster capable of scaling with global demand for energy-efficient, high-performance computing.

What this means for Asia and the broader semiconductor landscape

The Synopsys-A*STAR alliance signals a shift toward collaborative, regionalized innovation models where tool providers, research institutions and manufacturing players co-develop end-to-end solutions. For Asia’s semiconductor ambitions, such partnerships strengthen supply-chain depth, shorten innovation cycles and help localize critical know-how. Globally, the outcomes may accelerate the adoption of heterogeneous integration as the preferred path for delivering next-generation system capabilities.

Key takeaways

• Synopsys and A*STAR are combining EDA expertise with research and process facilities to fast-track advanced chip packaging in Asia.
• Focus areas include 2.5D/3D integration, chiplets, SiP, reliability modeling and materials innovation-backed by joint labs and RDKs.
• Workforce training and standards alignment are core to creating a durable regional ecosystem that can scale with global demand.
• The partnership aims to reduce risk and time-to-market for foundries, OSATs and fabless firms while accelerating practical deployments of heterogeneous integration across AI, automotive, 5G and data-center markets.